Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure

ABSTRACT

The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said layer of said first semiconductor material in said substrate, said buried layer having an upper surface and a lower surface and dividing said substrate into an upper part and a lower part; creating a buried damage layer; which at least partly adjoins and/or partly includes said upper surface of said buried layer; and removing said upper part of said substrate and said buried damage layer for exposing said buried layer. The invention also provides a corresponding layered semiconductor structure.

CROSS REFERENCE TO RELATED APPLICATIONS

Applicants claim priority under 35 U.S.C. §119(e) of U.S. Ser. No.60/328,759 filed Oct. 12, 2001. Applicants also claim priority under 35U.S.C. §365 of PCT/EP02/11423 filed Oct. 11, 2002. The internationalapplication under PCT article 21(2) was published in English.

The present invention relates to a method for forming a layeredsemiconductor technology structure having a layer of a firstsemiconductor technology material on a substrate of at least one secondsemiconductor technology material and to a corresponding layeredsemiconductor technology structure.

Moreover, the present invention relates to layered semiconductortechnology structure according to the preamble of claim 15 which isknown from Volz K. et al.: “Ion beam induced amorphisation andrecrystallisation of Si/SiC/Si layer systems” Nuclear Instruments &Methods in Physics Research, Section B. Beam Interactions With MaterialsAnd Atoms, North-holland Publishing Company. Amsterdam, N1 (01-12-1996),120 (1-4), pages 133-138 and from Lindner J K N et al.: “Controlling thedensity distribution of SiC nanocrystals for the ion beam synthesis ofburied SiC layers in silicon” Nuclear Instruments & Methods In PhysicsResearch, Section-B: Beam Interactions With Materials And Atoms,North-holland Publishing Company. Amsterdam, N1 (1999), 147 (1-4), pages249-255.

WO 01/72104 A1 discloses method for the production of silicon carbidelayers by means of ionic implantation of carbon and neals.

It should be mentioned that the term substrate as used herein is to beunderstood in a general form and should include all substrates known insemiconductor technology process technology, such as wafer substrates,layer substrates, well substrates, epitaxial substrates, SIMOXsubstrates, SOI substrates, silicon on sapphire substrates etc.

Moreover, semiconductor technology material is to be understood as anyconducting, semiconducting or isolating material used in semiconductortechnology processes.

Although applicable to other semiconductor technology materials, thepresent invention and ist underlying problems will be discussed withregard to a silicon carbide layer on a silicon substrate.

Silicon carbide (SiC) is a semiconductor technology material which, dueto its excellent physical properties combined with its technologicalcompatibility to established semiconductor technology processes andmaterials, has gained increasing industrial importance in the last tenyears.

A broad use of this semiconductor technology material, however, is sofar obstructed by problems of availability of crystal wafers or thinfilms having appropriate smooth surfaces as well as by the high priceresulting from the difficult manufacture of such crystal wafers and thinfilms, respectively. Nevertheless, some commercial semiconductortechnology products are already on the market, however, which haveenormously high prices. A broader scope of application of siliconcarbide is to be expected if the material problems regardingcost-efficient manufacture of epitaxial silicon carbide thin filmshaving large surfaces on inexpensive substrates are solved.

For the manufacture of silicon carbide, two standard processes areknown. The first process is a single crystal growth process, and thesecond process is a thin film epitaxy process. Technically, usefulsilicon carbide is only available from single crystal growth and fromhomoepitaxy of silicon carbide layers on expensive silicon carbidesingle crystals. However, no suitable method of realizingheteroepitaxial silicon carbide films on large area inexpensivesubstrates is known up to today.

FIGS. 6 a-c show a prior art process sequence for manufacturing asilicon carbide device known from U.S. Pat. No. 6,214,107 B1.

As shown in FIG. 6 a, the starting point of this process is an expensivesilicon carbide wafer 11.

In a first treatment step, as illustrated in FIG. 6 b, an implantation Iis performed for implanting ions in at least a part of a surface of saidsilicon carbide wafer 11 in order to introduce crystal defects in alayer 11 b near the crystal surface, leaving a substrate region 11 aundamaged.

In a second treatment step, an oxidation O is performed to form asilicon dioxide thin film in the implanted layer 11 b on the crystalsurface.

Finally, in a third step, as illustrated in FIG. 6 c, the silicondioxide thin film in the layer 11 b is removed by an etching processusing HF chemistry, resulting in a silicon carbide device of substrateregion 11 a having a cleaned surface of SiC.

A disadvantage of this known method is the fact that expensive siliconcarbide wafer substrates are needed. Moreover, the necessity of anoxidation step after the implantation treatment makes the known methodcomplicated.

Therefore, it is an object of the present invention to provide a lessexpensive and less complicated method for forming a layeredsemiconductor technology structure and an improved corresponding layeredsemiconductor technology structure having a smooth surface.

The method and structure according to the present invention contributeto a cost-efficient manufacture of epitaxial silicon carbide thin filmshaving large smooth surfaces on unexpensive substrates. Moreover, thestructure according to the present invention offers the advantage thatthe substrate manufacturer provides a semiprocessed structure which isfinished at the user. Here the upper layer serves as protection for theburied layer to be exposed later in a simple etching process.

The idea underlying the present invention is to provide a buried layerand thereafter to create a buried damage layer which at least partlyadjoins and/or at least partly includes an upper surface of said buriedlayer.

Preferred embodiments are listed in the respective dependent claims.

According to a preferred embodiment, said first semiconductor technologymaterial is silicon carbide and said second semiconductor technologymaterial is silicon.

According to another preferred embodiment, said step of burying isperformed by a first ion implantation step at a first temperaturefollowed by an optional annealing step.

According to another preferred embodiment, said step of creating aburied damage layer is performed by a second ion implantation step at asecond temperature.

According to another preferred embodiment, said step of removing saidupper part of said substrate and said buried damage layer is an etchingstep.

According to another preferred embodiment, said buried damage layeradjoins from below or includes said upper surface of said buried layersuch that a part of said buried layer belongs to said damage layer. Inthis case, said part is selectively etched in said etching step againstthe other part of said buried layer.

According to another preferred embodiment, the width of said damagelayer is varied along said upper surface of said buried layer. In thisway, a structure may be patterned into said damage layer which istransferred to the buried layer.

According to another preferred embodiment, said damage layer traversessaid buried layer in a laterally limited region.

According to another preferred embodiment, the width of said damagelayer is varied by performing a locally limited third ion implantationstep at a third temperature.

According to another preferred embodiment, the width of said damagelayer is varied by performing said second ion implantation step in alocally modulated way.

According to another preferred embodiment, said substrate comprises alayer of a third semiconductor technology material.

According to another preferred embodiment, said layer of said thirdsemiconductor technology material is a silicon oxide layer located undersaid buried layer.

According to another preferred embodiment, said layer of said thirdsemiconductor technology material is a doped silicon layer located undersaid buried layer.

According to another preferred embodiment, a LED structure is formed onsaid layered structure.

Embodiments of the present invention are illustrated in the accompanyingdrawings and described in detail in the following.

In the Figures:

FIGS. 1 a-e show a process sequence of a first embodiment of the methodaccording to the invention;

FIG. 2 shows a modification of the substrate of FIG. 1 in a secondembodiment of the method according to the invention;

FIGS. 3 a-c show a modification of the damage layer implantation step ofFIG. 1 in a third embodiment of the method according to the invention

FIGS. 4 a-c show a process sequence of a fourth embodiment of the methodaccording to the invention; and

FIG. 5 show a process sequence of a fifth embodiment of the methodaccording to the invention; and

FIGS. 6 a-c a prior art process sequence for manufacturing a siliconcarbide device known from U.S. Pat. No. 6,214,107 B1.

Throughout the figures, the same reference signs denote identical orfunctionally identical parts.

FIGS. 1 a-e show a process sequence of a first embodiment of the methodaccording to the invention.

The starting point of the first embodiment of the method according tothe present invention is a float zone silicon wafer 1, the main surfaceof which is denoted with reference sign 101 in FIG. 1 a.

In this example, the wafer 1 had a <100> orientation and was of n-typeconductivity (doped with phosphor) having a specific resistance of 1000Ωcm. However, it should be noted that also other wafer substrates havingdifferent orientations and/or dopings and/or differently grown wafers(f.e. Czochralsky) are suitable.

As illustrated in FIG. 1 b, carbon C is implanted in a firstimplantation step I1 at a temperature T1 such that a stoichiometricburied silicon carbide layer 5 is formed around the maximum of the Cdistribution. Said distribution is shown on the left-hand side of FIG. 1b and denoted ρ(x) where x is the penetration depth. After theimplantation step I1, the distribution can be fairly well described by aGaussian distribution.

For example, the implantation parameters are the following:

Dose: 8.5×10¹⁷ cm⁻²

Energy: 180 keV

Current density: 10 μAcm⁻²

Target temperature T1: 450° C.

The implantation step I1, however, results in a diffuse surface profileof the upper and lower surfaces 105, 104 of the implanted siliconcarbide layer 5, namely because of said Gaussian distribution. In otherwords, there is no sharp transition from SiC to an upper and lowersubstrate part 1 a, 1 b formed due to the presence of the buried layer5.

In order to have a box-shape distribution ρ′(x) reflecting a desiredsharp transition, as shown in FIG. 1 c, a thermal annealing step at atemperature T2 of 1250° C. for approximately 10 hours is performed in anargon atmosphere. This annealing step provides a homogeneous singlecrystal 3C-SiC layer having plane upper and lower surface 105, 104. Hereit should be noted that also other annealing conditions may beapplicable, f.e. temperatures between 1200° C. and 1350° C.

The manufacture of such a buried silicon carbide layer 5 by ion beamsynthesis using such conditions was disclosed first by J. K. N. Lindner,A. Frohnwieser, B. Rauschenbach and B. Stritzker, Fall Meeting of theMaterials Research Society, Boston, USA (1994), Mater. Res. Soc. Syn.Proc. Vol. 354 (1995), 171.

However, so far it was not possible to obtain a smooth epitaxial siliconcarbide surface layer 5 by simply removing the upper part 1 a of thesubstrate, either by chemical etching or by a chemical mechanicalpolishing process. Namely, due to the presence of silicon carbideprecipitations and/or surface clusters, the upper surface 105 of thesilicon carbide layer 5 always exhibited an undesired roughness.Experiments showed that in an attempt to remove the upper substratelayer f.e. by etching, SiC particles in random order are redeposited onthe substrate surface causing a very rough substrate surface.Presumably, due to the polar portion of the silicon carbide bounds,these particles very firmly adhere to the silicon carbide surface.

According to this embodiment of the present invention, as furtherexplained with reference to FIG. 1 d, this serious prior art problemcould be solved for the first time.

Theretofore, an implantation step I2 at a temperature T2 is performedwherein a damage layer 10, in this example an amorphous layer, having asharp interface to the single crystal silicon carbide of the buriedsilicon carbide layer 5 is created.

For said implantation step I2, the noble gas helium is used, namelybecause of its chemical inert behavior. However, in principle, alsoother ions may be used, e.g. hydrogen, oxygen, boron, phosphorous, neonetc.

For example, here the following implantation parameters for helium ionswere adopted:

Dose: 1.0×10¹⁷ cm⁻²

Energy: 50-55 keV

Current density: 10 μAcm⁻²

Target temperature: 100° C.

As clearly illustrated in FIG. 1 d, here the amorphous damage layer 10includes or embraces the upper surface 105 of the buried silicon carbidelayer 5. In other words, the amorphous damage layer 10 extends to a partof the upper part 1 a of the substrate and to a part 5 a of the buriedsilicon carbide layer 5.

By appropriate selection of the energy, ion-type, dose and targettemperature, it is possible to obtain a sharp interface between thecrystalline phase of the buried silicon carbide layer 5 and the damagedpart 5 a. Moreover, the penetration depth and width of the amorphousdamage layer 10 can be varied as desired.

Normally, a trade-off has to be found for the implantation temperatureT2 and the ion-type. F.e., if the implanted ions are comparably lightions, the temperature T2 should not be too high in order to avoid an insitu annealing. Heavy ion species exhibits the advantage that thenecessary dose (implantation time) may be drastically reduced. The ionenergy has to be enhanced for heavier ions because of their smallerpenetration depth. If the implantation temperature T2 is too low,however, the smoothness of the surfaces of the exposed silicon carbidelayer may be decreased.

In a next step, as illustrated in FIG. 1 e, the upper part of thesubstrate 1 a and the buried damage layer 10 are removed in an etch stepusing an etching solution containing HF/HNO₃ which is a standard etchingsolution in silicon process technology. Here, a mixing ratio of 1:6 hasproved to be very efficient. However, also other etching chemistryincluding other concentration ratios and/or other etchants may beapplied, such as KOH, TMAH, etc.

The etching time amounts to a few seconds, and the chemical reaction isselectively stopped on the crystalline part of the buried siliconcarbide layer 5. The time of the etching step is therefore not criticaland a robust process may be obtained.

As a result, a high quality Si/SiC substrate having the siliconsubstrate part 1 b and the remaining silicon carbide layer 5 isobtained, as illustrated in FIG. 1 e.

The main advantage of the obtained silicon carbide layer 5 after thisetching step is the smoothness of its surface. The reason is that SiCprecipitations in the upper substrate part 1 a near the surface 105 arecompletely etched away. Thus, SiC particles which are contained in theupper part of the substrate 1 a which lies above the buried siliconcarbide layer are not redeposited on the surface to the exposed, but arecontained in a damage layer and removed in the final etching step.Moreover, it is of advantage to remove a certain fraction of the buriedsilicon carbide layer by having an appropriate penetration depth of thedamage layer 10 into said silicon carbide layer 5 in order to provide anintermediate part of the buried SiC layer as new surface, because thispart is structurally better developed than the upper part and thereforeprovides best conditions for a smooth surface.

In a final treatment step which is not illustrated, a cleaning treatmentin deionized water for removing residuals of the etching solution may beperformed.

FIG. 2 shows a modification of the substrate of FIG. 1 in a secondembodiment of the method according to the invention.

As depicted in FIG. 2, the substrate 1′ comprises lower parts 1 b′ and 1c′, where 1 b′ denotes a silicon part and 1 c′ denotes a silicon dioxidepart. Such a substrate is known as SOI (silicon on insulator) substrate.

FIGS. 3 a-c show a modification of the damage layer implantation step ofFIG. 1 in a third embodiment of the method according to the invention.

According to the third embodiment shown in FIG. 3; a damage layer 10′ iscreated which does not penetrate into the buried silicon carbide layer5, but merely adjoins or stops at its upper surface 105.

Moreover, according to a further non-illustrated embodiment, the damagelayer could also adjoin the upper surface 105 from below or, in otherwords, be only contained in the buried silicon carbide layer 5.

FIGS. 4 a-c show a process sequence of a fourth embodiment of the methodaccording to the invention.

Regarding the fourth embodiment, the starting point is the structureshown in FIG. 1 c. However, here an implantation step I3 at thetemperature T3 is applied which does not produce a damage layer having aplane upper and lower surface, but a damage layer 10 which is modulatedin penetration depth. Particularly, the damage layer 10″ includes anintermediate portion 100″ which fully penetrates the buried siliconcarbide layer 5 and also enters the lower part of the substrate 1 b.This can be achieved by an ion beam implantation step 13 wherein thepenetration depth is modulated by locally changing the energy of the ionbeam without using any mask. The result of this implantation step 13 isshown in FIG. 4 a.

Another possibility for obtaining a modulated penetration depth would bethe use of two implantation steps where the first step corresponds to I2and the second step one has higher energy and is limited to theintermediate portion 100″ by means of a mask.

In the next step, the etching is performed with HF/HNO₃ as in the firstto third embodiments resulting in the structure shown in FIG. 4 b. Here,the exposed silicon carbide layer 5 is separated into two parts having adeep trench 100 separating said parts. The structure shown in FIG. 4 bis very well suited for micromechanical designs the manufacture of whichincludes an under-etching step for producing sensor parts suspended overthe substrate.

Such an under-etching step is illustrated with respect to FIG. 4 ccreating an under-etching region 110.

Here it should be noted that any structure can be patterned into saiddamage layer and then be transferred by etching to the SIC layer.

FIG. 5 show a process sequence of a fifth embodiment of the methodaccording to the invention.

According to the fifth embodiment shown in FIG. 5, the epitaxial siliconcarbide layer 5 on a substrate part 1 b′, 1 d′ of substrate 1′ is usedfor further process steps resulting in an LED structure (LED=LightEmitting Diode).

Here, the substrate part 1 b′ denotes a silicon wafer part, and thesubstrate part 1 d′ denotes a doped silicon part, which part is, forexample, obtained by an additional implantation step.

On top of the silicon carbide surface of the silicon carbide layer 5, anindium-aluminum-gallium-nitrogen layer is deposited on top of which ametallization layer 7 is provided for providing said light emittingdiode structure. Thus, the inventive method provides a suitablesubstrate for making LEDs in a non-expensive process sequence.

Instead of the substrate having substrate part 1 b′ as a silicon waferpart and substrate part 1 d′ as a doped silicon part, also a suitablyhighly doped substrate may be used.

Although the present invention has been described with regard tospecific embodiments, it is not limited thereto, but may be modified inmany ways.

Particularly, the described materials are only examples and replaceableby other suitable materials. The same is true for the etch processes.Also, the invention may be used for other semiconductor technologysubstrate layers.

Although, in the above embodiments, the implantation step has resultedin an amorphous buried damage layer, the present invention is notrestricted thereto. Of course, dependent on the implantation ion speciesand the other implantation parameters, also a certain degree of damagemay be sufficient to obtain a damage layer which can be easily removedin the etching step leaving back a smooth surface of the exposed siliconcarbide layer.

Here it should be mentioned that the first annealing step for convertingthe Gaussian profile into the box shape profile may be omitted, if theimplantation step for providing the buried damage layer enables to cutoff a sufficiently large portion of the tail of the Gaussiandistribution. This would further simplify the method for obtaining thesmooth silicon carbide surface.

Also the LED structure is merely an example of a broad variety ofpossible structures that can be formed on the layered semiconductortechnology structure according to the invention.

REFERENCE SIGNS

-   1,11 substrate-   101 substrate surface-   1 a,1 b,1 b′-   11 a,11 b substrate parts-   5 buried SiC layer-   104,105 surfaces of buried SiC layer-   I,I1-3 implantation step-   T1-3 implantation temperature-   ρ,ρ′ C density distribution-   10,10′,-   10″,100″ buried damage layer-   5 a part of 5 which belongs to 10-   103 lower surface of 1 c′-   1 c′ silicon dioxide layer-   110 underetch region-   100 trench-   1 d′ doped substrate region-   6 In—Ga—Al—N layer-   7 metallisation

1. A method for forming a layered semiconductor technology structurehaving a layer (5) of a first semiconductor technology material on asubstrate (1; 1′) of at least one second semiconductor technologymaterial, comprising the steps of: providing said substrate (1; 1′);burying said layer (5) of a first semiconductor technology material insaid substrate (1; 1′), said buried layer (5) having an upper surface(105) and a lower surface (104) and dividing said substrate (1; 1′) intoan upper part (1 a) and a lower part (1 b; 1 b′; 1 c); creating a burieddamage layer (10; 10′; 10″; 100″) which at least partly adjoins and/orat least partly includes said upper surface (105) of said buried layer(5); and removing said upper part (1 a) of said substrate (1; 1′) andsaid buried damage layer (10; 10′; 10″; 100″) for exposing said buriedlayer (5).
 2. The method according to claim 1, wherein said firstsemiconductor technology material is silicon carbide and said secondsemiconductor technology material is silicon.
 3. The method according toclaim 1, wherein said step of burying is performed by a first ionimplantation step (I1) at a first temperature (T1) followed by optionalannealing step (T2).
 4. The method according to claim 1, wherein saidstep of creating a buried damage layer (10; 10′; 10″; 100″) is performedby a second ion implantation step (I2) at a second temperature (T2). 5.The method according to claim 1, wherein said step of removing saidupper part (1 a) of said substrate (1; 1′) and said buried damage layer(10, 10′; 10″; 100″) is an etching step.
 6. The method according toclaim 5, wherein said buried damage layer (10; 10′; 10″; 100″) adjoinsfrom below or includes said upper surface (105) of said buried layer (5)such that a part (5 a) of said buried layer (5) belongs to said damagelayer (10; 10′; 10″; 100″) and wherein said part (5 a) is selectivelyetched in said etching step against the other part of said buried layer(5).
 7. The method according to claim 1, wherein the width of saiddamage layer (10; 10′; 10″; 100″;) is varied along said upper surface(105) of said buried layer (5).
 8. The method according to claim 7,wherein said damage layer (10; 10′; 10″; 100″;) traverses said buriedlayer (5) in a laterally limited region (100″).
 9. The method accordingto claim 7, wherein the width said damage layer (10; 10′; 10″; 100″;) isvaried by performing a locally limited third ion implantation step (I3)at a third temperature (T3).
 10. The method according to claim 7,wherein the width of said damage layer (10; 10′; 10″; 100″;) is variedby performing said second ion implantation step (I2) in a locallymodulated way.
 11. The method according to claim 1, wherein saidsubstrate (1; 1′) comprises a layer (1 c′, 1 d′) of a thirdsemiconductor technology material.
 12. The method according to claim 11,wherein said layer (1 c′, 1 d′) of said third semiconductor technologymaterial is a silicon oxide layer (1 c′) located under said buried layer(5).
 13. The method according to claim 11, wherein said layer (1 c′, 1d′) of said third semiconductor technology material is a doped siliconlayer (1 d′) located under said buried layer (5).
 14. The methodaccording to claim 13, further comprising the steps of: forming a LEDstructure on said layered structure.